1. Field of the Invention
This invention relates to the field of Field Programmable Gate Arrays (FPGAs). In particular it relates to a method and apparatus of extending the functionality of FPGAs by providing a means for the inclusion of user-specified functions through inclusion of other functional circuitry on the integrated circuit die with the FPGA circuitry, and particularly with such circuitry implemented as mask programmable circuit regions on the integrated circuit.
2. The Prior Art
An integrated circuit uses a network of metal interconnects between the individual semiconductor components which are patterned with standard photolithographic processes during wafer fabrication. Multiple levels of metallized patterns may be used to increase the flexibility of the interconnects.
It has long been recognized that a user-programmable interconnect technique or manufacturer programmability just prior to shipment would allow lower tooling costs and faster delivery time. To such an end, gate array circuits were developed.
A gate array circuit is an array of uncommitted gates with uncommitted wiring channels. To implement a particular circuit function, the circuit is mapped into the array and the wiring channels and appropriate connections are programmed to implement the necessary wiring connections that form the circuit function.
A gate array circuit can be programmed to implement virtually any set of functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from the user""s system, through input buffers, then through the circuit, and finally back out to the user""s system via output buffers. Such buffers provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation, or hysteresis.
If the wiring channels and appropriate connections are programmed by the manufacturer according to the construction masks, then the gate array circuit is described as a mask-programmable gate array.
If the wiring channels and appropriate connections arc programmed by the user according to programmable circuit elements, then the gate array circuit is described as an FPGA.
There are essentially two configurations of programmable circuit elements used to provide flexibility to the user for programming the FPGA. In the first configuration, an example of which is disclosed by El Gamal, et al. in U.S. Pat. No. 4,758,745, the FPGA can be permanently programmed by the user. In the second configuration, an example of which is disclosed by Freeman in U.S. Pat. No. 4,870,302, the FPGA can be changeably programmed by the user.
By comparison, a mask-programmable gate array offers higher functionality and performance and more efficient use of space while an FPGA offers lower design costs and greater user flexibility. Also, a mask-programmable gate array can implement any variety of I/O function and often at a higher speed than an FPGA. Other dedicated functional circuitry may also offer higher functionality and performance than its equivalent configured from FPGA components.
Accordingly, it is an object of the present invention to provide an improved FPGA which is capable of yielding the functionality, performance, and efficiency of a mask-programmable gate array while maintaining the lower design costs and user flexibility of an FPGA.
It is a further object of the present invention to provide an FPGA with the enhanced input/output capabilities offered by a mask-programmable gate array.
Yet another object of the present invention is to combine FPGA integrated circuit technology with that of oilier functional circuitry on the same integrated circuit die.
These and many other objects and advantages of the present invention will become apparent to one of ordinary skill in the art from a consideration of the drawings and ensuing description of the invention.
In accordance with the present invention, an enhanced FPGA is disclosed. A portion of an integrated circuit die includes dedicated functional circuitry or mask-programmable circuitry to provide critical circuit functions that cannot adequately or cost effectively be implemented using only Field Programmable manufacturing techniques.
A FPGA integrated circuit according to the present invention comprises a plurality of logic cells or logic modules placed in an array or matrix. The array has a set of vertical wiring channels and a set of horizontal wiring channels that are programmed by the user to interconnect the various logic cells to implement the required logic functions.
Connections to the wiring channels are made by user-programmable interconnect elements situated at the Intersection of any two wires to be connected. To make a connection, the user-programmable interconnect element is programmed, resulting in a low impedance electric connection between the two wires. Various types of user-programmable interconnect elements, such as antifuses, pass transistors, memory cells, non-volatile memory including flash, EEPROMs and EPROMs, may be employed in the architecture of the present invention.
To provide more efficient utilization of the wiring channels, a plurality of these programmable elements are used to segment the vertical and horizontal channels into shorter wire lengths. These segments may be joined together to form longer wire connections by programming the programmable elements or left as is to provide independent segment wire lengths and allow the same wiring channel position to be used several times for different circuit connections.
Programming circuitry is typically situated at the edge of the array. Programing g and connectivity information is shifted into the programming circuit, and appropriate voltages applied to effect the desired connection patterns. The same vertical and horizontal channels that are used for wiring channels in normal operations may be used for programming the various interconnections and to provide complete testing of the array modules and wiring paths. Alternately, direct programming of individual elements may be performed. The various circuits and processes for programming user-programmable interconnect elements are well known in the art and are not a part of the present invention. Details of programming are not presented here in order to avoid unnecessarily complicating the disclosure.
The logic modules used in the FPGA portion of the array may be universal logic elements, which are very efficient in its implementation of random logic functions defined by the use of selected user-programmable elements. Persons of ordinary skill in the art will appreciate that numerous different modules are available. ACT-290
At least one portion of the array is not populated by logic modules but instead includes other circuitry. In one embodiment of the invention, the other circuitry comprises a mask-programmable circuit, such as a mask-programmable gate array. Other specific embodiments of the invention include circuits such as analog blocks (A/D, D/A, voltage reference, op amps, comparators, PLL, DPLL, DLL, crystal oscillators), specialized digital blocks (SRAM, DRAM, ROM, PROM, EPROM, EEPROM, FIFO, multiplexers, microprocessors, embedded controllers, ALU, floating point processor. DSP, array processor), and specialized I/O functions (GTL, PECL, LVDS, bus controllers for PCI, ISA, EISA, RAMBUS, etc., network transceivers, high speed serial connections).
Interface circuitry allows connections to be made between the mask-programmable circuit, the logic modules in the array, and I/O circuitry connecting to I/O pins on the integrated circuit. According to one aspect of the present invention, one or more logic module locations at or near the interface between the FPGA portion and the mask-programmable portion of the integrated circuit are populated by interface circuits for making connections between FPGA portion and the mask-programmable portion of the integrated circuit.
The end user chooses from a wide range of functions and specifies them to the manufacturer. The manufacturer in turn programs some functions into the integrated circuit using mask-programmable techniques, leaving the user to program other functions into the integrated circuit using the field programmable portion of the integrated circuit.
In one embodiment of the present invention, the mask-programmable portion of the integrated circuit contains a gate array for implementing a wide range of functions. The mask-programmable gate array is connected to the FPGA via a circuit interface portion of the integrated circuit. The circuit interface can contain either mask-programmable or Field Programmable circuits for controlling and processing the signals passing from and to both the mask-programmable gate array and the FPGA. Each of the mask-programmable gate array, the FPGA, and the circuit interface are connected to an I/O portion of the integrated circuit. The I/O portion of the integrated circuit can contain either mask-programmable or Field Programmable circuits for controlling and processing the signals passing into the integrated circuit from external sources or out of the integrated circuit to external sources.
In an alternative embodiment of the present invention, the mask-programmable portion of the integrated circuit contains I/O circuits for implementing a wide range of functions for controlling and processing the signals passing into the integrated circuit from external sources or out of the integrated circuit to external sources. The mask-programmable I/O circuits are connected to the FPGA via a circuit interface portion of the integrated circuit. The circuit interface can contain either mask-programmable or Field Programmable circuits for controlling and processing the signals passing from and to the FPGA. Both the circuit interface and the FPGA can also receive signals from and send signals to external sources directly.
Those skilled in the art will recognize the general applicability of the mask-programmable enhanced FPGA disclosed herein to other types of circuits, both analog and digital.